1. Field of the Invention
The present invention relates to a memory control device, and more particularly to a memory control device which is able to interface with a memory device regardless of the address information format for reading out data stored therein.
2. Description of the Prior Art
There is a conventional system for displaying image data stored in a memory device as a static image such as a letter on a display device of a raster scan system of a cathode ray tube (CRT), for example, a teletext sytem and a videotex system. In these systems, it is necessary to control the generation of horizontal and vertical synchronizing signals and of address information for the memory for reading out the image data to be displayed on an image screen of the CRT from the memory in synchronization with the electron beam position of the CRT and for displaying it. A memory control device is used for performing the above operation.
Either a dynamic RAM (D-RAM) or a static RAM (S-RAM) is generally used in the memory device described above. The D-RAM is less expensive and has a large memory capacity, but the access time is slow. Further the D-RAM has the disadvantage that it requires a large number of other components for operating it as a parallel unit because the D-RAM usually has a one bit structure. On the other hand, the S-RAM has a fast access time. But it is more expensive, small in memory capacity and large in power dissipation. However, the S-RAM usually has an advantage in that it requires fewer components when used as a parallel unit because the S-RAM has a parallel bit structure, e.g., 8-bit parallel.
As described above, both the S-RAM and the D-RAM have respective merits and demerits for use in a memory device. A choice between the D-RAM and the S-RAM is made in accordance with the needs of each system. Therefore, the memory control device which can interface with either type of RAM has good utility and wide application.
Interfaces for address information are different between the D-RAM and the S-RAM. The D-RAMs have a large memory capacity as described above so that they are apt to have a large number of connection pins in accordance with the number of address lines. Therefore, in a conventional D-RAM, the memory is divided in two or more sections and fewer address lines are used in common by the divided memory sections for a time-shared operation system to decrease the number of connection pins.
For example, taking a memory device of 64K words (K designates 2.sup.10 bits and one word consists of 16-bits), the address information requires 16-bits. In the D-RAM, a 16-bit address is divided into two units of 8-bits and these 8-bit units are inputted in a time-shared operation as a row address and a column address respectively. In the S-RAM, on the other hand, a 16-bit address consisting of the row address and the column address is inputted by one unit.
As described above, a conventional memory control device has the disadvantage that it must be modified for the particular memory device in accordance with the difference in address information format.